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все задержки принято указывать для переходов в высокое и низкое состояние
stresses
el.
All delays are characterized for both rising and falling transitions
(см.
Digital Integrated Circuits – A Design Perspective 2/e by Jan M. Rabaey
,
Anantha Chandrakasan
,
Borivoje Nikolić
2003
ssn
)
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